High density circuit assemblies are typically formed as sequentially added layers of circuitry on printed circuit boards (PCBs), metal sheets, ceramic substrates, and the like. Such assemblies are typically formed by full additive metalization, for example, by electroless or electrolytic plating or vacuum deposition. Full metalization processes are time consuming and suffer yield problems due to the inherent thickness non-uniformity of the circuitry. Also, it is generally necessary to drill through holes and blind vias as separate intermediate operations during the manufacturing process, adding to the cost of manufacture.
U.S. Pat. No. 5,260,518, issued to Tanaka, discloses a method for forming multi-layer circuit boards in which stepped holes, increasing in diameter from lower to upper conductive layers, are bored or drilled during manufacture of the assembly. The holes provide conductive interconnection between electrical circuits disposed on different layers of the assembly. The increasingly larger diameters of the holes are required to solve the problem of misregistration of the holes when the layers are laminated. This not only increases the cost and complexity of manufacture, but the larger holes also limit the spacing, or density, of interconnection sites in the electronic circuit assembly. The circuits have lower component density, which requires larger board areas and increases the overall size of the assembly.
Other methods of forming multiple-layered electronic circuit assemblies require adhesive materials to bond the electrically conductive circuit layers to dielectric materials that separate the circuit layers. U.S. Pat. No. 4,420,364, issued to Nukii, describes the use of high-insulation adhesive sheets in the construction of multiple layer circuit assemblies. U.S. Pat. No. 5,234,536, issued to Parthasarathi, discloses the use of adhesive materials to bond a metal foil layer to a substrate. In each of these constructions, holes must be provided through the adhesive materials so that selected portions of separated circuit layers can be interconnected. These holes must be sufficiently large so that adhesive reflow during lamination does not occlude the interconnection site. When relatively large holes are required for circuit interconnection, the density of vias and other interconnection sites is limited. Electronic circuit assemblies formed through the use of adhesive bonding materials generally require more space for positioning of components, producing relatively large board areas and increased size of electronic circuits formed thereon.
U.S. Pat. No. 5,665,650, issued to Lauffer and incorporated herein by reference, discloses a method for manufacturing multiple layered electronic circuit assemblies that does not require adhesive bonding materials or stepped holes of increasing diameter to provide for conductive interconnection between electrical circuits. Because the via and inter-connection holes through the dielectric material can be relatively small, high-density circuitry on the circuit layers can be formed. The manufacturing system for the formation of multiple-layered, high-density electronic circuit assemblies is economical and easily automated so that previous problems with registration of respective circuits on spaced-apart layers are reduced.
Because one or more photoimageable dielectric layers and one or more electrically conductive layers are sequentially laminated to a preformed multi-layer printed circuit board during manufacture, however, a problem arises during via definition or filling. This problem typically causes the entire multi-layer structure, which includes the substrate and all the attached layers, to be scrapped. Thus, a need exists for a method that retains all of the advantages of this method, but does not require that the entire multi-layer structure be scrapped when a problem occurs during manufacture.